1. Field of the Invention
The present invention relates to semiconductor storage devices, and more particularly to a composite semiconductor storage device including a programmable memory.
2. Description of the Background Art
Programmable non-volatile semiconductor storage devices includes a UVEPROM (Ultra-Violet ray erasable Electrically reprogrammable Read Only Memory) whose contents are erasable by ultraviolet radiation and are also rewritable, and an EEPROM (Electrically Erasable and Programmable ROM) whose contents are electrically rewritable. These programmable ROMs are used in systems as program storage memories or data storage memories.
A ROM writer 200 as shown in FIG. 9 is used for programming such programmable ROMs.
The ROM writer 200 is connected to a device 300 including a programmable ROM. The ROM writer 200 includes an address generator 210, a data memory 220, a control signal generator 230, a comparing and checking circuit 240, a constant voltage generator 250 and a basic clock generator 260. The basic clock generator 260 applies a basic clock signal to the address generator 210 and control signal generator 230. In response to the basic clock signal, the address generator 210 generates an address signal AD. The control signal generator 230, in response to the basic clock signal, generates control signals such as a chip enable signal CE and an output enable signal OE. The data memory 220 stores data for writing and expected value data. The comparing and checking circuit 240 compares data D read from the device 300 and the expected value data stored in the data memory 220. The constant voltage generator 250 generates a source voltage Vcc, a high voltage for writing Vpp and ground voltage GND.
When programming the device 300, it is first checked whether all the address regions of the ROM in the device 300 are in erased condition. In practice, data are read from all the address regions of the ROM, and are compared in the comparing and checking circuit 240 with expected data "0" or "1" for the erased condition stored in the data memory 220. This is called a blank check.
Next, the data for writing stored in the data memory 220 are written successively into the address regions of the ROM in the device 300. This is called programming.
Finally, the data are read successively from the ROM in the device 300, which are compared in the comparing and checking circuit 240 with the expected value data stored in the data memory 220. It is thereby checked whether the data have been written correctly into the ROM. This is called a verifying process.
In this way, programming is carried out for a device including a programmable ROM.
Marked progress has been made recently in the micro fabrication technique in wafer processing. Further, in order to achieve lightness and compactness, it is desired to minimize the number of components. With this in view, composite ICs have been developed which have a plurality of memories such as a RAM (Random Access Memory) and a ROM, an operational unit and the like integrated on a single chip. FIG. 10 shows a conventional semiconductor storage device as an example of such composite ICs, in which an EPROM and an SPROM (Static Random Access Memory) are integrated on a single chip.
The semiconductor storage device 100a shown in FIG. 10 includes an EPROM (hereinafter called the ROM) 1 and an SRAM (hereinafter called the RAM) 3. An input/output buffer 2 is provided for the ROM 1, and an input/output buffer 4 for the RAM 3. Further, an input/output buffer 5 is provided to act as an I/0 port.
An address buffer/address decoder (hereinafter called the address buffer/decoder) 6 receives an externally applied address signal AD, and outputs an address signal AD1 to the ROM 1 and RAM 3. Further, the address buffer/decoder 6 generates a select signal CSROM for selecting the ROM 1, a select signal CSRAM for selecting the RAM 3, and a select signal CSPORT for selecting the input/output buffer 5 (I/0 port). A control circuit 7 receives externally applied control signals, such as a chip enable signal CE and an output enable signal OE, and generates a read signal RD and a write signal WR. At a time of data writing (programming), a high voltage for writing Vpp is externally applied to the ROM 1.
The input/output buffers 2, 4 and 5 are connected to a common data bus 8. An input/output buffer 9a also is connected to the data bus 8.
The way in which the semiconductor storage device of FIG. 10 operates will be described with reference to FIG. 11 showing waveforms.
The ROM 1, RAM 3 and input/output buffer 5 have their own address regions allocated thereto, respectively. When the address signal AD shows an address in the address region corresponding to the ROM 1, the address buffer/decoder 6 sets the select signal CSROM to "H" and the select signals CSRAM and CSPORT to "L". As a result, the input/output buffer 2 becomes operable. Further, a memory element in the ROM 1 is accessed in accordance with the address signal AD1.
At a data reading time, the control circuit 7 generates the read signal RD. This places the input/output buffer 2 and input/output buffer 9a in output enable state. As a result, the data read from the accessed memory element is output through the input/output buffer 2, data bus 8 and input/output buffer 9a.
At a data writing time, the control circuit 7 generates the write signal RD. This places the input/output buffer 2 and input/output buffer 9a in input enable state. As a result, an externally applied data D is written into the accessed memory element through the input/output buffer 9a, data bus 8 and input/output buffer 2.
When the externally applied address signal AD denotes an address in the address region corresponding to the RAM 3, the select signal CSRAM attains "H" and the select signals CSROM and CSPORT attain "L". As a result, the input/output buffer 4 becomes operable. Further, a memory element in the RAM 3 is accessed in accordance with the address signal AD1. As in the foregoing process, the data stored in the accessed memory element is read and output, or externally applied data D is written into the accessed memory element.
When the address signal AD denotes an address in the address region corresponding to the input/output buffer 5, the select signal CSPORT attains "H" and the select signals CSROM and CSRAM attain "L". As a result, data D applied externally is input to the data bus 8 through the input/output buffer 5, or a data on the data bus 8 is output through the input/output buffer 5. Alternatively, data D applied externally may also be input to the data bus 8 through the input/output buffer 9a, or a data on the data bus 8 output through the input/output buffer 9a. In this way, the input/output buffer 5 acts as an I/0 port.
If the ROM 1 in the conventional semiconductor storage device 100a has the same storage capacity as a general-purpose ROM already in wide use, the ROM 1 may be programmed using the commercially available ROM writer 200 (programming device) such as shown in FIG. 9.
Chip size of a composite IC such as the semiconductor storage device 100a inevitably becomes large. Further, the number of signals is increased, since varied functions are provided on a single chip. In a composite IC, therefore, the number of terminals differs from that of a general-purpose ROM and so does the package. Under the circumstances, programming of the ROM 1 is achieved by using an appropriate pin-converting adapter to match the specification of ROM writer 200.
However, the ROM 1 mounted in the above semiconductor storage device often has a storage capacity different from that of a general-purpose ROM. For example, a general-purpose ROM has a storage capacity of 32K bytes (1 byte=8 bits) or 64 kbytes, while the ROM 1 mounted in the above semiconductor storage device may have a storage capacity of 20K or 40K bytes. In such a case, the following problem arises when programming the ROM.
The ROM writer 200 effects write and read controls suited to a general-purpose ROM having a larger storage capacity than the ROM 1 mounted on the above semiconductor storage device 100a. Consequently, when a blank check is carried out, access is made also to address regions other than that corresponding to the ROM 1. In other words, a data writing operation and a data reading operation are effected also for the addresses assigned to the RAM 3, input/output buffer 5 and others.
When a blank check or verification is carried out, expected data are not read from the address regions other than that corresponding to the ROM 1. Thus, the comparing and checking circuit 240 in the ROM writer 200 gives the result of comparison as a "mismatch". As a result, the ROM writer 200 decides that programming is impossible, and discontinues the programming operation.
It will be appreciated that, if the ROM 1 mounted on the semiconductor storage device 100a differs in storage capacity from a general-purpose ROM, programming cannot be effected with the commercially available ROM writer 200.
When programming the above semiconductor storage device, therefore, it is necessary to use a pin-converting adapter as noted hereinbefore and to re-install software or hardware for the ROM writer to program only the address region corresponding to the built-in ROM. Alternatively, a larger tester device of higher performance than the commercially available ROM writer must be used to program only a desired address region.
Thus, the ROM writer must be re-installed or an overpriced tester device must be purchased each time the ROM in the above semiconductor storage device is programmed.